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Monday, January 31, 2011

Transistors in Transition

As the semiconductor industry prepares for the 15/14 nm node and beyond, the most revolutionary change in chip architecture is likely to take place. I have been fortunate to hear of many of these possible developments at recent SEMI events, such as SEMICON Korea (Dr. Yoshio Nishi, Stanford), ISS (Paulo Gargini, Intel) and SMC (Nobu Koshiba, President, JSR).

Two main alternatives now being considered by the leading-edge logic makers: vertical devices (FinFETs), and fully depleted planar transistors based on extremely thin SOI (FD-ETSOI) substrates. Further out, researchers are moving from silicon channels to germanium and III-V materials in heterogeneous ICs. Vertical transistors offer the potential for high performance, while presenting several manufacturing challenges. The transistors based on thin SOI substrates also have advantages and challenges. Can wafers with these thin layers be provided with consistent material thicknesses, at acceptable wafer costs?

Industry researchers are also discussing alternatives to today’s charge-based memories, including resistive RAMs (RRAMs), spin-torque transfer RAMs (STT-RAMs), and phase-change memories (PC-RAMs). Memory companies are confident they can advance NAND flash chips by putting memory cells on top of each other. These cell array transistor (CAT) memories could link 16-32 memory cells, taking NAND well beyond the 20 nm generation.

Nobu Koshiba, President, JSR Corporation, said during the keynote of the Strategic Materials Conference, “We are leaving the Materials Era and entering the Architecture Era…the evolution of CMOS devices will be driven by new architectures.”

Characterizing the new era will be diversified pathways to extend scaling, including 3D IC, extended CMOS through FinFET and other innovative structures, beyond-CMOS technologies such as nanotubes, graphene and other non-silicon possibilities, and new application or “fusion devices.” The pathway for logic may include FinFET structures with gate last integration. Challenges to overcome include metal fill through small structure, strained gate, and high temperature resistant dielectric fills that will require new deposition and material approaches.

In addition to 3D, DRAM and NAND pathways may include MRAM and ReRAM that will require new conduction path formation, resistivity change approaches, and the discovery of resistive film materials which enable high performance memory with simple planer stacking and/or cross point structure. New device structures may require magnetic materials with high thermal stability, low temperature (< 250°C) cure dielectrics, and low temperature (< 250°C) deposition of metal through PVD, electro plating, and/or electroless.

At ISS, Paulo Gargini discussed recent research that demonstrated how Ge can achieve high mobility and high drive current, and how Ge -well field effect transistor would be viable p channel option for low power III V CMOS architecture. Carbon nanotubes, graphene ribbons and other graphene approaches are also getting attention at Intel.

I am not a PhD so I can’t fully appreciate all the issues involved in vertical transistors, III V materials or new memory technologies. I think I do appreciate, however, the implications for the supply chain. Traditional scaling has impacted equipment, subsystems and components on a narrow range of parameters. While it drove an equipment and systems upgrade business coincident with Moore’s Law, many of the changes centered around lithography and structure dimensions. These new architecture changes will affect materials, temperatures and process characteristics in every way possible. The R&D challenges are going to be enormous and the collaboration requirements in the industry are going to skyrocket. Big research breakthroughs are going to trickle down to new equipment specifications, new instrumentation, even new vacuum pumps, and more. We will probably see some new suppliers enter the business, and some old ones lose market share.

It sure makes for an exciting industry--both now as we try to forecast which way the industry will go, and in the future as companies develop solutions they think will be meet new customer requirements.

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