WANTED: Integration Across The Supply Chain

The need for better design, production and test integration had been discussed in the semiconductor industry for over 10 years. The concept had been repeated so many times, in so many contexts, that it’s taken on the feel of a shallow aphorism, like the saying “power tends to corrupt” or “he who laughs last, laughs best”

But the need for better supply chain integration has finally emerged as a real necessity with meaningful and specific attributes.

To meet consumers need for cramming more functionality into smaller, cheaper cell phones and multimedia devices, chip designers need an integrated design solution that lets them optimize interdie and die-to-substrate connectivity for signal performance and manufacturability. A key part of this process lies in co-design opportunities between the IC and package, the package and printed-circuit board or both-in order to satisfy tough performance, cost and size goals. Design for Manufacturing (DFM) has become an essential component in the production process and many see a future when DFM ceases to be independent step, but integrated directly into the design and verification process. New technologies such Through Silicon Vias (TSVs) also require an unprecedented integration between design, manufacturing and multi die packaging.

The fact is there is no forum today that brings together chip designers, wafer processing engineers, packaging specialists, and test plan developers under one roof to talk about the growing set of interdependencies and co-design needs.

We are trying to do that at SEMICON West.

Because Silicon Valley is the home of so many fabless semiconductor firms, consumer product companies like Apple and HP and Cisco, and leading IDMs like Intel, SEMICON West is the natural center of the emerging collaborative development model. SEMICON West already is one of the largest EDA expositions in the world with over 3000 attendees interested in design automation (including hundreds of CTOs) and exhibitors such as Synopsis, Magma and Cadence. And, most of the large US mobile and consumer products companies attend West, as well as every major IDM and fabless semiconductor company in the world.

The next step is to develop programs and forums to encourage and nurture collaboration and that is what we’ve done, especially this year. Some of the programs that leveraging this need for design-production-packaging-test collaboration include:

• IDMs, OSATs, EDA suppliers, packaging equipment firms, and wafer processing companies will meet in comprehensive Packaging Sumitt to discuss the product, market and supply chain implications of 3D TSVs


• High Density Packaging will dominate the TAP TechXPOT on Tuesday, July 15 from 3:00pm–5:00pm.


• The increasing complexity of microelectronic devices is bringing about new thinking around semiconductor test. The new methodologies and ideas around test that will require industry collaboration and cooperation will be discussed on both Tuesday and Wednesday.


• The synergy between anew materials and new processes for 32 and 22 nm manufacturing will highlight the Wafer Processing TechXPOT.


• The linkage between lower power design and DFM will be addressed on the Thursday keynote by Jim Miller of Cadence.


• DFM and the increasing complexity of “manufacturing sign-off” will be address throughout Thursday.


• Standards committee meetings—where collaboration takes place at the highest, most substantive level—will be held throughout SEMICON

If you have any ideas on how we can do better—at SEMICON West or any other SEMI program-- in bringing the increasingly interdependent elements of the supply chain together, please let me know.